Fujitsu F2MCTM-16LX Bedienungsanleitung Seite 438
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CHAPTER 20 LIN-UART
20.7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1)
When LIN-UART is used in operation mode 0 (normal mode) or operation mode 1
(multiprocessor mode), the asynchronous transfer mode is selected.
■ Operation in Asynchronous Mode
●
Transfer data format
Generally each data transfer in the asynchronous mode operation begins with the start bit (low-level) and
ends with at least one stop bit (high-level). The direction of the bit stream (LSB first or MSB first) is
determined by the BDS bit of the Serial Status Register (SSR). The parity bit (if enabled) is always placed
between the last data bit and the (first) stop bit.
In operation mode 0 the length of the data frame can be 7 or 8 bits, with or without parity, and 1 or 2 stop
bits.
In operation mode 1 the length of the data frame can be 7 or 8 bits with a following address-/data-selection
bit instead of a parity bit. 1 or 2 stop bits can be selected.
The calculation formula for the bit length of a transfer frame is:
Length = 1 + d + p + s
(d = number of data bits [7 or 8], p = parity [0 or 1], s = number of stop bits [1 or 2]
Figure 20.7-1 shows the data format in the asynchronous mode.
- MB90360 Series 1
- HARDWARE MANUAL 1
- CONTENTS 9
- CHAPTER 1 17
- OVERVIEW 17
- 1.1 Overview of MB90360 18
- ■ Product overview 21
- ■ Features 23
- CHAPTER 1 OVERVIEW 25
- 1.3 Package Dimensions 28
- 1.4 Pin Assignment 29
- 1.5 Pin Functions 30
- 1.6 Input-Output Circuits 33
- CMOS input 36
- Automotive input 36
- Standby control fo 36
- 1.7 Handling Device 37
- X0 (X0A) 38
- X1 (X1A) 38
- CHAPTER 2 43
- 2.1 Outline of the CPU 44
- 2.2 Memory Space 45
- ■ Address generation types 47
- 2.3 Memory Map 48
- 2.4 Linear Addressing 49
- 2.5 Bank Addressing Types 50
- 2.7 Registers 53
- H RP x 10H 55
- 2.7.1 Accumulator (A) 56
- 2.7.3 Processor Status (PS) 58
- B4 B3 B2 B1 B0 : RP 59
- Initial value 0 0 0 0 0 59
- ILM2 ILM1 ILM0 : ILM 60
- Initial value 0 0 0 60
- 2.7.4 Program Counter (PC) 61
- 2.8 Register Bank 62
- DTB register 63
- DPR register 63
- 24-bit physical address 63
- 2.9 Prefix Codes 64
- CHAPTER 2 CPU 66
- MOV ILM,#imm8 66
- • • • • • • • • 67
- • • • • •• • • • • 67
- Instructions 68
- CHAPTER 3 71
- PS I ILM 72
- MC-16LX CPU 72
- ■ Software Interrupts 73
- ■ Exceptions 74
- 3.2 Interrupt Vector 75
- 3.4 Interrupt Flow 81
- CHAPTER 3 INTERRUPTS 82
- 3.5 Hardware Interrupts 83
- MC-16LX bus 85
- 3.5.3 Multiple interrupts 87
- 3.6 Software Interrupts 88
- ■ Others 89
- ■ Structure 91
- (Undefined 93
- when reset) 93
- Intelligent I/O Service (EI 95
- 3.9 Exceptions 98
- CHAPTER 4 99
- DELAYED INTERRUPT 99
- GENERATION MODULE 99
- − : Undefined 101
- S Interrupt 101
- :Undefined 102
- Address: 00009F 102
- R/W : Read/Write R/W 103
- : Reset value 103
- Interrupt 104
- CHAPTER 5 107
- 5.1 Clocks 108
- ■ Clock Supply Map 110
- CHAPTER 5 CLOCKS 111
- PLL clock multiplier 114
- 5.5 Clock Mode 119
- ■ Machine Clock 120
- Microcontroller 124
- CHAPTER 6 125
- CLOCK SUPERVISOR 125
- CHAPTER 6 CLOCK SUPERVISOR 127
- Reserved 129
- ■ Sub-clock Mode 132
- ■ Stop Mode 132
- CHAPTER 7 135
- 7.1 Resets 136
- Synchronization 141
- 7.4 Reset Operation 142
- ■ Mode Fetch 143
- 7.5 Reset Cause Bits 144
- R : Read only 145
- W : Write only 145
- X : Undefined 145
- 7.6 Status of Pins in a Reset 148
- CHAPTER 8 149
- LOW-POWER 149
- CONSUMPTION MODE 149
- Watch timer 153
- Timebase timer 153
- To watchdog timer 153
- 00011000B 155
- : Read/WriteR/W 155
- : Write onlyW 155
- 1-instruction 158
- 8.5 Standby Mode 159
- 8.5.1 Sleep Mode 161
- ■ Return from Sleep Mode 162
- 8.5.2 Watch Mode 164
- 8.5.3 Timebase Timer Mode 166
- 8.5.4 Stop Mode 168
- ■ Return from Stop Mode 169
- 8.6 Status Change Diagram 171
- ■ Clock Mode Switching 174
- Enter the Standby Mode 174
- CHAPTER 9 177
- MEMORY ACCESS MODES 177
- 9.1.1 Mode Pins 179
- 9.1.2 Mode Data 180
- General 181
- ■ Recommended Setting 182
- CHAPTER 10 183
- I/O PORTS 183
- 10.1 I/O Ports 184
- 10.2 I/O Port Registers 185
- CHAPTER 10 I/O PORTS 186
- 76543210 190
- R/W: Read/Write 191
- ILSR1 : 00000FH 192
- ILSR0 : 00000EH 192
- ■ Initial value of ILSR 193
- CHAPTER 11 195
- TIMEBASE TIMER 195
- ■ Clock Supply 197
- : Undefined 200
- 1XX00100B 201
- CHAPTER 11 TIMEBASE TIMER 205
- ■ Supply of Operation Clock 207
- CHAPTER 12 211
- WATCHDOG TIMER 211
- ■ Functions of Watchdog Timer 212
- CHAPTER 12 WATCHDOG TIMER 215
- Start up 215
- 12.3 Watchdog Timer Registers 217
- CHAPTER 13 225
- 16-Bit I/O TIMER 225
- CHAPTER 13 16-Bit I/O TIMER 230
- ■ Pins of 16-bit I/O Timer 232
- 00000000B 234
- R/WR/WR/WR/WR/WR/W R/WR/W 234
- Reset value 239
- IEI0IEI1ICUS0ICUS1 240
- IEI2IEI3 240
- XXX0X0XXB 240
- XXXXXXXXB 240
- OS Function 244
- ■ Correspondence to EI 244
- ". The counter 245
- ICPnICPm 247
- CHAPTER 14 253
- 16-BIT RELOAD TIMER 253
- ■ Operation at Underflow 255
- Prescaler 256
- Output signal 256
- ■ Pins of 16-bit Reload Timer 258
- (TMCSR:L) 261
- 00000000 263
- XXXXXXXX 265
- Counter clock 272
- Data load signal 272
- 2T to 2.5T 273
- Reload data 274
- ■ Setting of Event Count Mode 275
- CHAPTER 15 283
- WATCH TIMER 283
- 15.1 Overview of Watch Timer 284
- ■ Cycle of Clock Supply 285
- Address: 0000AA 288
- 45321067 289
- R/WR/WR/WR/W R/WR/WRR/W 289
- CHAPTER 15 WATCH TIMER 290
- 15.4 Watch Timer Interrupt 291
- : Used bit 292
- : Unused bit 292
- CHAPTER 16 297
- 8-/16-BIT PPG TIMER 297
- PPGCD: REV 301
- PPGEF: REV 301
- (Low level 302
- (High level side) 304
- (Low level side) 304
- ■ Pins of 8-/16-bit PPG Timer 306
- PEN0 PE0 PIE0 PUF0 308
- PEN1 PE1 PIE1 310
- PUF1 MD1 MD0 310
- T × (L + 1) 316
- T × (H + 1) 316
- T × (L0 + 1) × (L1+ 1) 325
- + 1) × (H1 + 1) 325
- T × (L0 + 1) T × (H0 + 1) 325
- Note: n = C, E 328
- CHAPTER 17 329
- DTP/EXTERNAL 329
- INTERRUPTS 329
- : Read/Write 337
- INT9R INT8R 341
- MOD2 MOD1 343
- RELDMOD0 OUTE OUTL 343
- Peripheral data 346
- Processing and interrupt 346
- ■ External Interrupt Function 347
- 17.4.2 DTP Function 348
- CHAPTER 18 355
- 8-/10-BIT A/D CONVERTER 355
- A/D data 357
- Comparator 357
- Figure 18.5-1 376
- Figure 18.5-2 378
- 18.5.3 Pause-conversion Mode 380
- 18.5.4 Conversion Using EI 382
- CHAPTER 19 387
- LOW VOLTAGE DETECTION/ 387
- CPU OPERATING 387
- DETECTION RESET 387
- 4.0V ± 0.3V 388
- Detection voltage 388
- C (approx.262ms) 389
- Reset Circuit 390
- Register 392
- R/W:Read Write 392
- :Initial value 392
- CHAPTER 20 397
- LIN-UART 397
- 20.1 Overview of LIN-UART 398
- ■ LIN-UART operation modes 400
- ■ LIN-UART interrupt and EI 401
- ■ Block Diagram of LIN-UART 403
- 20.3 LIN-UART Pins 407
- 20.4 LIN-UART Registers 408
- CHAPTER 20 LIN-UART 409
- SR0:000023 413
- SR1:00002B 413
- D0D1D2D3D4D5D6D7 415
- Initial value 421
- R/W : Read/Write 421
- 20.5 LIN-UART Interrupts 422
- (RDRF = "1") 425
- 20.6 LIN-UART Baud Rates 429
- 20.6.1 Setting the Baud Rate 431
- ■ Using external clock 433
- ■ Counting Example 433
- 20.7 Operation of LIN-UART 436
- ■ Inter-CPU Connection Method 437
- ■ Synchronization Methods 437
- ■ Signal Mode 437
- ■ Operation Enable Bit 437
- ST : Start bit 439
- SP : Stop mode 439
- P: Parity bit 439
- AD : Address/data bit 439
- (ECCR:SSM=1,SCR:PEN=0) 442
- LIN bus timing 447
- ■ LIN-UART Direct Pin Access 448
- Data transmission 450
- SCRn, SMRn 451
- SSRn, TDRn/RDRn 451
- ESCRn, ECCRn 451
- LBL1 LBL0 454
- (Operation Mode 3) 455
- 20.8 Notes on Using LIN-UART 457
- CHAPTER 21 459
- CAN CONTROLLER 459
- ■ Features of CAN Controller 460
- CSR1 (High) 469
- • Function control by writing 470
- CHAPTER 21 CAN CONTROLLER 474
- ■ Register Configuration 477
- ■ Register Function 477
- ■ Prescaler Settings 479
- 21.4.10 IDE Register (IDER) 482
- 21.4.23 Message Buffers 497
- CAN bus 506
- ■ Acceptance Filtering 506
- ■ Storing Received Message 506
- ■ Receive Overrun 507
- ■ Completing Reception 508
- To set the F 511
- Address: 518
- ■ Setting of CAN Direct Mode 520
- CHAPTER 22 521
- ADDRESS MATCH 521
- DETECTION FUNCTION 521
- AD1EAD2E AD0E 523
- AD4EAD5E AD3E 523
- Function 532
- ■ System Configuration and E 533
- PROM Memory Map 533
- ■ Setting and Operating State 535
- CHAPTER 23 541
- ROM MIRRORING MODULE 541
- Internal data bus 542
- : Undefined 543
- XXXXXXX1B 544
- 1213 11 10 9 8 544
- CHAPTER 24 545
- 512K-BIT FLASH MEMORY 545
- RDYINT WE RDY 546
- MB90F362/T(S) 548
- MB90F367/T(S) 548
- 24.3 Write/Erase Modes 549
- Automatic algorithm 553
- RDYINT bit 553
- 1 Machine cycle 553
- ■ Command Sequence Table 554
- ■ Data Polling Flag (DQ7) 557
- 24.6.2 Toggle Bit Flag (DQ6) 558
- 24.7.2 Writing Data 562
- 24.9 Flash Security Feature 567
- CHAPTER 25 569
- Supply Used) 573
- Supplied from Programmer) 575
- Write control pin 576
- Figure 25.4-1 577
- CHAPTER 26 581
- ROM SECURITY FUNCTION 581
- APPENDIX 583
- APPENDIX A I/O Maps 584
- Abbreviation 586
- APPENDIX B Instructions 592
- B.1 Instruction Types 593
- B.2 Addressing 594
- ■ Effective Address Field 595
- ■ Direct Addressing 596
- Memory space 597
- specified in an operand.) 601
- Before execution 603
- After execution 603
- : Highest bitMSB 605
- : Lowest bitLSB 605
- B.5 Execution Cycle Count 609
- B.6 Effective address field 612
- MC-16LX Instruction List 616
- APPENDIX B Instructions 617
- B.9 Instruction Map 630
- Table B.9-2 Basic Page Map 632
- ■ Data Read by Read Access 652
- 3rd bus cycle 654
- Data polling 654
- • The address is FxAAAA 655
- at erasing sector 655
- DQ6 to DQ0 = 656
- DQ7 to DQ0 = 656
- ■ RST and RY/BY Timing 657
- Write/erase command sequence 659
- to FFFFFF 660
- ■ List of Interrupt Vectors 660
- FUJITSU LIMITED 681
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