Fujitsu F2MCTM-16LX Bedienungsanleitung Seite 222

  • Herunterladen
  • Zu meinen Handbüchern hinzufügen
  • Drucken
  • Seite
    / 682
  • Inhaltsverzeichnis
  • LESEZEICHEN
  • Bewertet. / 5. Basierend auf Kundenbewertungen
Seitenansicht 221
206
CHAPTER 12 WATCHDOG TIMER
Checking reset factors
The reset factor bits in the watchdog timer control register (WDTC: PONR, WRST, ERST, SRST) can be
read after a reset to check the reset factors.
Figure 12.4-2 Relationship between Clear Timing and Interval Time of Watchdog Timer
Reference: For details on the reset factor bit, see "CHAPTER 7 RESETS".
ab cd
Clock
selector
Reset
circuit
[Watchdog timer block diagram]
2-division
circuit
Count enable
output circuit
2-division
circuit
2-bit counter
WTE bit
Count enable and clear
[Minimum interval time] When clear WTE bit immediately before rising of count clock.
Count clock a
2-division’s value b
2-division’s value c
Count enable
Reset signal d
Count start
Counter clear
7
×
(Count clock cycle/2)
WTE bit clear
Watchdog reset generation
[Maximum interval time] When clear WTE bit immediately after rising of count clock.
Count clock a
2-division’s value b
2-division’s value c
Count enable
Reset signal
Count start
Counter clear
9
×
(Count clock cycle/2)
WTE bit clear
Watchdog reset generation
Reset
signal
Seitenansicht 221
1 2 ... 217 218 219 220 221 222 223 224 225 226 227 ... 681 682

Kommentare zu diesen Handbüchern

Keine Kommentare