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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.49 LSR2 (Logical Shift to the Right Direction)
Makes a logical right shift of the word data in "Ri" by "{u4 + 16}" bits, stores the result
to "Ri".
■ LSR2 (Logical Shift to the Right Direction)
Assembler format: LSR2 #u4, Ri
Operation: Ri >> {u4 + 16} → Ri
Flag change:
N: Cleared
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last.
Execution cycles: 1 cycle
Instruction format:
Example: LSR2 #8, R3
NZVC
0C–C
MSB LSB
10110001 u4 Ri
R3 R3
0000 00FFFFFF FFFF
NZVC
CCR CCR
NZVC
00010000
Instruction bit pattern : 1011 0001 1000 0011
Before execution After execution
- FR Family 1
- INSTRUCTION MANUAL 1
- ■ Trademark 5
- ■ Organization of this manual 6
- CONTENTS 9
- Main changes in this edition 15
- CHAPTER 1 25
- FR FAMILY OVERVIEW 25
- CHAPTER 1 FR FAMILY OVERVIEW 27
- CHAPTER 2 29
- MEMORY ARCHITECTURE 29
- 2.1 FR Family Memory Space 30
- 2.1.1 Direct Address Area 31
- 2.1.2 Vector Table Area 32
- 2.2 Bit Order and Byte Order 34
- 2.3 Word Alignment 35
- CHAPTER 3 37
- REGISTER DESCRIPTIONS 37
- 3.2 General-purpose Registers 39
- ● R14 (Frame Pointer: FP) 40
- ● R15 (Stack Pointer: SP) 40
- 3.3 Dedicated Registers 41
- 3.3.1 Program Counter (PC) 42
- 3.3.2 Program Status (PS) 43
- Initial value: --00XXXXB 45
- ■ Note on PS Register 46
- Bit no 48
- 3.3.4 Return Pointer (RP) 49
- ■ Return Pointer Functions 50
- CHAPTER 4 55
- RESET AND "EIT" 55
- PROCESSING 55
- 4.1 Reset Processing 57
- ■ Vector Table Configuration 59
- ■ Saved Registers 60
- ■ Recovery from EIT handler 60
- 4.3 Interrupts 61
- 4.3.1 User Interrupts 62
- ■ How to Use User Interrupts 63
- 4.4 Exception Processing 66
- 4.5 Traps 68
- 4.5.3 Step Trace Traps 71
- 4.5.5 Coprocessor Error Trap 73
- 4.6 Priority Levels 75
- CHAPTER 5 77
- PRECAUTIONARY 77
- INFORMATION FOR THE FR 77
- FAMILY CPU 77
- 5.1 Pipeline Operation 78
- Generated Deleted 79
- 5.3 Register Hazards 80
- ■ Interlocking 81
- CHAPTER 6 87
- INSTRUCTION OVERVIEW 87
- 6.1 Instruction Formats 88
- CHAPTER 7 91
- DETAILED EXECUTION 91
- INSTRUCTIONS 91
- 10100100 i4 Ri 97
- 10100101 i4 Ri 98
- Register) 100
- 10100000 i4 Ri 101
- 10100001 i4 Ri 102
- Destination Register) 103
- 10101101 Rj Ri 104
- 10101001 i4 Ri 108
- 10000100 Rj Ri 110
- Example: AND R2, @R3 111
- 10000101 Rj Ri 112
- Example: ANDH R2, @R3 113
- 10000110 Rj Ri 114
- Example: ANDB R2, @R3 115
- 10010100 Rj Ri 117
- Example: OR R2, @R3 118
- 10010101 Rj Ri 119
- Example: ORH R2, @R3 120
- 10010110 Rj Ri 121
- Example: ORB R2, @R3 122
- 10011100 Rj Ri 124
- Example: EOR R2, @R3 125
- Data in Memory) 126
- Example: EORH R2, @R3 127
- 10011110 Rj Ri 128
- Example: EORB R2, @R3 129
- Example: BANDL #0, @R3 131
- Example: BANDH #0, @R3 133
- Example: BORL #1, @R3 135
- Example: BORH #1, @R3 137
- Example: BEORL #1, @R3 139
- Example: BEORH #1, @R3 141
- 10001000 u4 Ri 142
- 10001001 u4 Ri 143
- 7.34 MUL (Multiply Word Data) 144
- Example: MUL R2, R3 145
- 10101011 Rj Ri 146
- Example: MULU R2, R3 147
- 10111111 Rj Ri 148
- Example: MULH R2, R3 149
- 10111011 Rj Ri 150
- Example: MULUH R2, R3 151
- 100101110100 Ri 152
- 100101110101 Ri 154
- DIV0U and DIV1 x 32 156
- Example: DIV1 R2 157
- 100101110111 Ri 158
- Example: DIV2 R2 159
- 1001111101100000 160
- 1001111101110000 161
- 10110110 Rj Ri 162
- 10110100 u4 Ri 163
- "Ri" 164
- 10110010 Rj Ri 165
- 10110000 u4 Ri 166
- 10110001 u4 Ri 167
- 10111010 Rj Ri 168
- 10111001 u4 Ri 170
- 8765 43210000 0000 171
- 0005 43210000 0000 172
- 0000 00210000 0000 173
- 00000100 Rj Ri 174
- 00000000 Rj Ri 175
- 0010 Rio8 176
- 00000011 u4 Ri 177
- 000001110000 Ri 178
- 000001111000 Rs 179
- Example: LD @ R15 +, MDH 180
- 0000011110010000 181
- Example: LD @ R15 +, PS 182
- 00000101 Rj Ri 183
- 00000001 Rj Ri 184
- 0100 Rio8 185
- 00000110 Rj Ri 186
- 00000010 Rj Ri 187
- 0110 Rio8 188
- 00010100 Rj Ri 189
- 00010000 Rj Ri 190
- 0011 Rio8 191
- 00010011 u4 Ri 192
- 000101110000 Ri 193
- 000101111000 Rs 194
- 0001011110010000 195
- 00010101 Rj Ri 196
- 00010001 Rj Ri 197
- 0101 Rio8 198
- 00010110 Rj Ri 199
- 00010010 Rj Ri 200
- 0111 Rio8 201
- 8765 43218765 4321 205
- 8765 4321 205
- Status Register) 206
- FFF3 F8D5 FFF3 F8D5 207
- FFF3 F8D5 207
- 7.87 JMP (Jump) 208
- FF80 0000 FF80 0122 209
- FF80 0004 209
- 7.89 CALL (Call Subroutine) 210
- 1001011100100000 211
- 7.91 INT (Software Interrupt) 212
- Example: INT #20H 213
- 1001111100110000 214
- Example: INTE 215
- 1001011100110000 216
- Example: RETI 217
- 1110 cc rel8 219
- 7.95 JMP:D (Jump) 220
- 7.96 CALL:D (Call Subroutine) 221
- 7.97 CALL:D (Call Subroutine) 223
- 1001111100100000 225
- 1111 cc rel8 228
- 00001000 229
- 00011000 230
- Address) 231
- Example: DMOV @88H, @R13+ 232
- Example: DMOV @R13+, @54H 234
- Instruction bit pattern : 236
- Example: DMOV @R15+, @38H 238
- Example: DMOVH @88H, @R13+ 242
- Example: DMOVH @R13+, @52H 244
- 00001010 245
- 00011010 246
- Example: DMOVB @71H, @R13+ 248
- Example: DMOVB @R13+, @57H 250
- 10111100 u4 Ri 251
- 10111101 u4 Ri 252
- 100111111100 u4(n+0) 253
- CRiCRjCC(n+2) 253
- 0000000100110100 254
- (CPU register) 256
- (Coprocessor register) 256
- 8343 834C8343 834A 261
- 10000011 262
- 10010011 263
- 11111 10100 264
- 10100011 265
- 100101111000 Ri 266
- 100101111001 Ri 267
- 100101111010 Ri 268
- 100101111011 Ri 269
- 10001100 270
- Example: LDM0 (R3, R4) 271
- 10001101 272
- 10001110 274
- Example: STM0 (R2, R3) 275
- 10001111 276
- 7.133 ENTER (Enter Function) 278
- 7.134 LEAVE (Leave Function) 280
- Example: LEAVE 281
- 10001010 Rj Ri 282
- APPENDIX 285
- APPENDIX A Instruction Lists 286
- ● Symbols in Operation Column 287
- ● Format Column 288
- ● OP Column 288
- ● Cycle (CYC) Column 288
- ● FLAG Column 288
- A.2 Instruction Lists 289
- → o8=disp8 292
- → o8=disp9 >> 1 292
- → o8=disp10 >> 2 292
- → u4=udisp6 >> 2 292
- → rel8=(label9 – PC – 2)/2 294
- → rel11=(label12 – PC – 2)/2 294
- → dir=dir8 296
- → dir=dir9 >> 1 296
- → dir=dir10 >> 2 296
- → s8=s10 >> 2 297
- → u8=u10 >> 2 297
- APPENDIX B Instruction Maps 298
- B.1 Instruction Map 299
- B.2 "E" Format 300
- 32-BIT MICROCONTROLLER 313
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