Fujitsu Semiconductor Controller MB89950/950A Handbücher

Bedienungsanleitungen und Benutzerhandbücher für Kommunikation Fujitsu Semiconductor Controller MB89950/950A.
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Fujitsu Semiconductor Controller MB89950/950A Bedienungsanleitung (318 Seiten)

Marke: Fujitsu | Kategorie: Kommunikation | Größe: 4.64 MB |

Englisch

Inhaltsverzeichnis

MB89950/950A Series

1

HARDWARE MANUAL

1

■ Trademarks

5

■ Structure of This Manual

5

READING THIS MANUAL

7

CONTENTS

11

CHAPTER 1

15

OVERVIEW

15

CHAPTER 1 OVERVIEW

18

Internal bus

21

1.5 Pin Assignment

22

■ MQP-64C-P01 pin assignment

23

1.6 Package Dimensions

24

For ROM chip enable

28

CHAPTER 2

31

HANDLING DEVICES

31

2.1 Notes on Handling Devices

32

Verify program

33

CHAPTER 2 HANDLING DEVICES

34

CHAPTER 3

35

3.1 Memory Space

36

■ Memory map

37

3.1.1 Special Areas

38

to FFFF

39

■ Storing 16-bit data in RAM

40

■ Storing 16-bit operands

40

3.2 Dedicated Registers

41

CCR initial value

43

X011XXXX

43

Low (no interrupt)

44

3.3 General-purpose Registers

47

3.4 Interrupts

49

3.4.2 Interrupt Processing

51

3.4.3 Multiple Interrupts

53

Interrupt handling

54

Interrupt processing routine

54

Address Memory

55

General

56

3.5 Resets

57

With reset output

59

Without reset output

59

3.5.2 Reset Operation

60

3.5.3 Pin States during Reset

62

3.6 Clocks

63

Free-run counter

64

3.6.1 Clock Generator

65

Main clock

66

MB89950/950A series

66

3.6.2 Clock Controller

67

■ Instruction cycle (t

68

3.7.2 Sleep Mode

73

3.7.3 Stop Mode

74

CHAPTER 3 CPU

75

■ State transition diagrams

77

H Selects single-chip mode

81

CHAPTER 4

83

I/O PORTS

83

4.1 Overview of I/O Ports

84

4.2 Port 0

86

■ Port 0 register

87

4.2.2 Operation of Port 0

89

4.3 Port 1

91

■ Port 1 register

92

4.3.2 Operation of Port 1

94

4.4 Port 2

96

■ Port 2 register

97

4.4.2 Operation of Port 2

99

4.5 Port 3

100

PDR (Port data register)

101

■ Port 3 register

102

4.5.2 Operation of Port 3

104

4.6 Port 4

106

PDR read

107

4.6.2 Operation of Port 4

110

MB89950/950A

112

CHAPTER 5

113

TIMEBASE TIMER

113

■ Clock supply function

115

3456 9 10111213141516171819

116

CHAPTER 5 TIMEBASE TIMER

117

TBTC register

117

5.4 Timebase Timer Interrupt

120

: Used bit

121

1 : Set “1”

121

0 : Set “0”

121

■ Operation of timebase timer

122

CHAPTER 6

125

WATCHDOG TIMER

125

■ Watchdog timer function

126

————WTE3 WTE2 WTE1 WTE0

127

CHAPTER 6 WATCHDOG TIMER

128

WDTC register

128

W : Write-only

129

— : Unused

129

X : Indeterminate

129

CHAPTER 7

135

8-BIT PWM TIMER

135

■ PWM timer function

137

CHAPTER 7 8-BIT PWM TIMER

138

■ 8-bit PWM timer registers

141

■ PWM control register (CNTR)

142

■ PWM compare register (COMR)

144

H 80H)*

146

For PWM timer function

150

Counter value

151

Count clock

151

Coding example

153

CHAPTER 8

155

PULSE WIDTH COUNT

155

TIMER (PWC)

155

= (4/5 MHz) x 221

156

= 176.8 s

156

Automatic clear

172

Reactivate

172

■ Measuring long pulse widths

174

NCCR NCS1 NCS0

176

: Unused bit

176

Operation

177

Cycle of

178

CHAPTER 9

183

8-BIT SERIAL I/O

183

■ Serial I/O function

184

CHAPTER 9 8-BIT SERIAL I/O

185

Overflow

185

■ 8-bit serial I/O registers

188

■ Serial mode register (SMR)

190

SDR 001DH XXXXXXXX

193

R/W : Readable and writable

193

■ Serial output operation

195

9.6 Operation of Serial Input

197

#0 #1 #2 #3 #4 #5 #6 #7

199

Cleared by the program

199

Interrupt request

199

■ Using external shift clock

200

SCK input

201

SIOF bit

201

SO pin output

201

Idle state

202

External shift clock

202

8-bit data transfer

202

CHAPTER 10

207

10.1 Overview of UART

208

CH/2/4 min.)

211

10.2 Structure of UART

213

CHAPTER 10 UART

215

10.3 UART Pins

216

10.4 UART Registers

218

R/W R/W R/W R/W R/W

227

: Unused

227

10.5 UART Interrupts

229

10.6 Operation of UART

230

■ Transmit operation

231

■ Receive operation

232

10.8 Program Example for UART

234

CHAPTER 11

237

EXTERNAL INTERRUPT

237

CIRCUIT (EDGE)

237

Internal data bus

240

Cleared at the same time

245

Processing description

246

CHAPTER 12

247

LCD CONTROLLER/DRIVER

247

Internal bus

249

■ Internal voltage divider

251

and V3 pins

253

■ External voltage divider

253

Mask option

256

Port/SEG selection signal

256

■ LCD controller/driver RAM

257

12.3.3 Display RAM

262

Other than "00B"

264

Operation (1/2 Duty Ratio)

265

LCD Panel

267

Display RAM

267

Segment No

267

Operation (1/3 Duty Ratio)

268

LCD Panel

270

Operation (1/4 Duty Ratio)

271

APPENDIX

277

APPENDIX A I/O Map

278

Lower 4 bits

281

(8 bits)

282

B.2 Addressing

283

H + FFFEH

287

B.3 Special Instructions

288

MC-8L Instructions

293

■ Arithmetic instructions

295

C --> A

296

C <-- A

296

■ Branch instructions

298

■ Other instructions

299

B.6 Instruction map

300

APPENDIX C Mask Options

301

And EPROM Microcontroller

303

EPROM Microcontrollers

304

305

■ Bit map for PROM option

306

■ Programming yield

307

■ Pin states in various modes

309

FUJITSU LIMITED

317

Fujitsu Geräte