Fujitsu MHD2032AT Bedienungsanleitung

C141-E050-02ENMHC2032AT, MHC2040ATMHD2032AT, MHD2021ATDISK DRIVESPRODUCT MANUAL

C141-E050-02EN vImportant Alert ItemsImportant Alert MessagesThe important alert messages in this manual are as follows:A hazardous situation could re

5.3 Host CommandsC141-E050-02EN 5-29At command issuance (I/O registers setting contents)1F7H(CM)0 0 0 1xxxx1F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(SN)1

Interface5-30 C141-E050-02ENAt command issuance (I/O registers setting contents)1F7H(CM)0 1 1 1xxxx1F6H(DH)×L×DVHead No. /LBA [MSB]1F5H(CH)1F4H(CL)1F3

5.3 Host CommandsC141-E050-02EN 5-31At command issuance (I/O registers setting contents)1F7H(CM)1 0 0 1 0 0 0 11F6H(DH)× × ×DVMax. head No.1F5H(CH)1F

Interface5-32 C141-E050-02ENAt command issuance (I/O registers setting contents)1F7H(CM)1 1 1 0 1 1 0 01F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(S

5.3 Host CommandsC141-E050-02EN 5-33Word ValueDescription20 X’0000’Undefined21 X’0000’Undefined22 X’0004’Number of ECC bytes transferred at READ LONG

Interface5-34 C141-E050-02ENWord ValueDescription69-79X’00’Reserved80 X’000E’Major version number *1181 X’0000’Minor version number (not reported)82

5.3 Host CommandsC141-E050-02EN 5-35*3 Word 23-26: Firmware revision; ASCII code (8 characters, Left-justified)*4 Word 27-46: Model name;ASCII code

Interface5-36 C141-E050-02ENTable 5.4 Information to be read by IDENTIFY DEVICE command (3 of 3)*9 Word 63: Multiword DMA transfer modeBit 15-8: Curre

5.3 Host CommandsC141-E050-02EN 5-37Bit 0 = 1 Mode 0*14 WORD 128Bit 15-9: ReservedBit 8: Security level. 0: High, 1: MaximumBit 7-5: ReservedBit

Interface5-38 C141-E050-02EN(14) SET FEATURES (X’EF’)The host system issues the SET FEATURES command to set parameters in theFeatures register for th

5.3 Host CommandsC141-E050-02EN 5-39At command issuance (I/O registers setting contents)1F7H(CM)1 1 1 0 1 1 1 11F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(

Interface5-40 C141-E050-02ENSingle word DMA transfer mode X 00010 000 (X’10’: Mode 0)00010 001 (X’11’: Mode 1)00010 010 (X’12’: Mode 2)Multiword

5.3 Host CommandsC141-E050-02EN 5-41At command issuance (I/O registers setting contents)1F7H(CM)1 1 0 0 0 1 1 01F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(

Interface5-42 C141-E050-02ENWord 47Bit 7-0 = 10:Word 59 = 0000:= 00xx:Maximum number of sectors that can be transferred per interruptby the READ MULTI

5.3 Host CommandsC141-E050-02EN 5-43Table 5.6 Diagnostic codeCodeResult of diagnosticX’01’X’03’X’05’X’8x’No error detected.Data buffer compare errorR

Interface5-44 C141-E050-02ENcommand is used for checking ECC function by combining with the WRITELONG command.Number of ECC bytes to be transferred is

5.3 Host CommandsC141-E050-02EN 5-45This command is operated under the following conditions:• The command is issued in a sequence of the READ LONG or

Interface5-46 C141-E050-02ENAt command issuance (I/O registers setting contents)1F7H(CM) 1 1 1 1 0 1 0 01F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(

5.3 Host CommandsC141-E050-02EN 5-47At command issuance (I/O registers setting contents)1F7H(CM)1 1 1 1 1 0 0 01F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(

Interface5-48 C141-E050-02ENSector Count register valuePoint of timer0[X’00’]30 minutes1 to 3 [X’01’ to X’03’]15 seconds4 to 240 [X’04’ to X’F0’](Valu

C141-E050-02EN viiContentsCHAPTER 1 Device Overview... 1-11.1 Features 1-21.1

5.3 Host CommandsC141-E050-02EN 5-49(22) IDLE IMMEDIATE (X’95’ or X’E1’)Upon receipt of this command, the device sets the BSY bit of the Status regi

Interface5-50 C141-E050-02ENUnder the standby mode, the spindle motor is stopped. Thus, when the commandinvolving a seek such as the READ SECTOR(s) c

5.3 Host CommandsC141-E050-02EN 5-51At command issuance (I/O registers setting contents)1F7H(CM)X’94’ or X’E0’1F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(S

Interface5-52 C141-E050-02ENAt command issuance (I/O registers setting contents)1F7H(CM)X’99’ or X’E6’1F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC

5.3 Host CommandsC141-E050-02EN 5-53At command issuance (I/O registers setting contents)1F7H(CM)X’98’ or X’E5’1F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(S

Interface5-54 C141-E050-02ENTable 5.7 Features Register values (subcommands) and functionsFeatures ResisterFunctionX’D0’SMART Read Attribute Values:A

5.3 Host CommandsC141-E050-02EN 5-55Features ResisterFunctionX’DA’SMART Return Status:When the device receives this subcommand, it asserts the BSY bi

Interface5-56 C141-E050-02ENAt command completion (I-O registers setting contents)1F7H(ST)Status information1F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(SN)1

5.3 Host CommandsC141-E050-02EN 5-57Table 5.9 Format of insurance failure threshold value dataByteItem0001Data format version number02Attribute 1Attr

Interface5-58 C141-E050-02ENAttribute IDAttribute name12Number of power-on-power-off times13 to 198(Reserved)199Ultra ATA CRC error rate200Write error

Contentsviii C141-E050-02ENCHAPTER 3 Installation Conditions...3-13.1 Dimensions 3-23.2

5.3 Host CommandsC141-E050-02EN 5-59Bit 7: If this bit is 1, it indicates that the automatic off-line datacollection function is enabled.Status ByteM

Interface5-60 C141-E050-02EN• Check sumTwo’s complement of the lower byte, obtained by adding 511-byte data onebyte at a time from the beginning.• Ins

5.3 Host CommandsC141-E050-02EN 5-61Table 5.10 Contents of security passwordWordContents0Control wordBit 0: Identifier0 = Compares the user password

Interface5-62 C141-E050-02ENAt command issuance (I-O register contents)1F7h(CM)1 1 1 1 0 0 1 11F6h(DH)× × ×DVxx1F5h(CH)1F4h(CL)1F3h(SN)1F2h(SC)1F1h(FR

5.3 Host CommandsC141-E050-02EN 5-63At command issuance (I-O register contents)1F7h(CM)1 1 1 1 0 1 0 01F6h(DH)× × ×DVxx1F5h(CH)1F4h(CL)1F3h(SN)1F2h(S

Interface5-64 C141-E050-02EN• READ DMA• WRITE DMA• SECURITY DISABLE PASSWORD• READ LONG• WRITE LONG• SECURITY FREEZE LOCK• READ MULTIPLE• WRITE MULTIP

5.3 Host CommandsC141-E050-02EN 5-65(32) SECURITY SET PASSWORD (F1h)This command enables a user password or master password to be set.The host trans

Interface5-66 C141-E050-02ENTable 5.12 Relationship between combination of Identifier and Security level, andoperation of the lock functionIndentifier

5.3 Host CommandsC141-E050-02EN 5-67Issuing this command in FROZEN MODE returns the Aborted Command error.At command issuance (I-O register contents)

Interface5-68 C141-E050-02ENAt command issuance (I-O register contents)1F7h(CM)111001111F6h(DH)× × ×DVxx1F5h(CH)1F4h(CL)1F3h(SN)1F2h(SC)1F1h(FR)xxxxxx

ContentsC141-E050-02EN ix4.6.1 Read/write preamplifier (PreAMP) 4-94.6.2 Write circuit 4-104.6.3 Read circuit 4-124.6.4 Digital PLL circui

5.3 Host CommandsC141-E050-02EN 5-69Table 5.13 Command code and parameters (2 of 2)Command nameError register (X’1F1’)Status register (X’1F7’)BBK UNC

Interface5-70 C141-E050-02EN5.4 Command ProtocolThe host should confirm that the BSY bit of the Status register of the device is 0prior to issue a com

5.4 Command ProtocolC141-E050-02EN 5-71words, the host should receive the relevant sector of data (512 bytes of uninsureddummy data) or release the D

Interface5-72 C141-E050-02ENsector in multiple-sector reading. If the timing to read the Status register does not meetabove condition, normal data tr

5.4 Command ProtocolC141-E050-02EN 5-73b) The host writes a command code in the Command register. The drive sets theBSY bit of the Status register.c)

Interface5-74 C141-E050-02ENNote:For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order toclear INTRQ (interrupt)

5.4 Command ProtocolC141-E050-02EN 5-75Figure 5.6 Protocol for the command execution without data transfer5.4.4 Other commands• READ MULTIPLE• SLEEP•

Interface5-76 C141-E050-02ENf) When the command execution is completed, the device clears both BSY andDRQ bits and asserts the INTRQ signal. Then, th

5.5 Ultra DMA Feature SetC141-E050-02EN 5-775.5 Ultra DMA Feature Set5.5.1 OverviewUltra DMA is a data transfer protocol used with the READ DMA and W

Interface5-78 C141-E050-02ENBoth the host and device perform a CRC function during an Ultra DMA burst. Atthe end of an Ultra DMA burst the host sends

Contentsx C141-E050-02EN5.5.2 Phases of operation 5-785.5.2.1 Ultra DMA burst initiation phase 5-785.5.2.2 Data transfer phase 5-795.5.2.3

5.5 Ultra DMA Feature SetC141-E050-02EN 5-79g) Ultra DMA data in burstThe device should not invert the state of this signal in the period from themome

Interface5-80 C141-E050-02ENf) Once the transmitting side has outputted the ending request, the output stateof STROBE signal should not be changed unl

5.5 Ultra DMA Feature SetC141-E050-02EN 5-819) The host shall negate STOP and assert HDMARDY- within tENV afterasserting DMACK-. After negating STOP

Interface5-82 C141-E050-02EN3) The device shall resume an Ultra DMA burst by generating a DSTROBEedge.b) Host pausing an Ultra DMA data in burst1) The

5.5 Ultra DMA Feature SetC141-E050-02EN 5-837) If DSTROBE is negated, the device shall assert DSTROBE within tLIafter the host has asserted STOP. No

Interface5-84 C141-E050-02EN5) The host shall assert STOP no sooner than tRP after negatingHDMARDY-. The host shall not negate STOP again until after

5.5 Ultra DMA Feature SetC141-E050-02EN 5-855.5.4 Ultra DMA data out commands5.5.4.1 Initiating an Ultra DMA data out burstThe following steps shall o

Interface5-86 C141-E050-02ENHSTROBE edge no more frequently than tCYC for the selected Ultra DMAMode. The host shall not generate two rising or falli

5.5 Ultra DMA Feature SetC141-E050-02EN 5-875.5.4.4 Terminating an Ultra DMA data out bursta) Host terminating an Ultra DMA data out burstThe followin

Interface5-88 C141-E050-02ENb) Device terminating an Ultra DMA data out burstThe following steps shall occur in the order they are listed unless other

ContentsC141-E050-02EN xiCHAPTER 6 Operations... 6-16.1 Device Response

5.5 Ultra DMA Feature SetC141-E050-02EN 5-8913) The host shall neither negate STOP nor HSTROBE until at least tACK afternegating DMACK-.14) The host s

Interface5-90 C141-E050-02ENNote: Since no bit clock is available, the recommended approach forcalculating CRC is to use a word clock derived from th

5.5 Ultra DMA Feature SetC141-E050-02EN 5-915.5.6 Series termination required for Ultra DMASeries termination resistors are required at both the host

Interface5-92 C141-E050-02EN5.6 Timing5.6.1 PIO data transferFigure 5.10 shows of the data transfer timing between the device and the hostsystem.

5.6 TimingC141-E050-02EN 5-93Figure 5.10 Data transfer timing

Interface5-94 C141-E050-02EN5.6.2 Single word DMA data transferFigure 5.9 show the single word DMA data transfer timing between the deviceand the host

5.6 TimingC141-E050-02EN 5-955.6.3 Multiword DMA data transferFigure 5.10 shows the multiword DMA data transfer timing between the deviceand the host

Interface5-96 C141-E050-02EN5.6.4 Transfer of Ultra DMA dataFigures 5.13 to 5.22 define the timings concerning every phase for the Ultra DMABurst.Tabl

5.6 TimingC141-E050-02EN 5-975.6.4.2 Ultra DMA data burst timing requirementsTable 5.16 Ultra DMA data burst timing requirements (1 of 2)NAMEMODE 0(i

Interface5-98 C141-E050-02ENTable 5.16 Ultra DMA data burst timing requirements (2 of 2)NAMEMODE 0(in ns)MODE 1(in ns)MODE 2(in ns)COMMENTMIN MAX MIN

Contentsxii C141-E050-02ENIllustrationsFiguresFigure 1.1 Current fluctuation (Typ.) at +5V when power is turned on 1-6Figure 2.1 Disk drives outer

5.6 TimingC141-E050-02EN 5-995.6.4.3 Sustained Ultra DMA data in burst5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes.Not

Interface5-100 C141-E050-02EN5.6.4.4 Host pausing an Ultra DMA data in burst5.6.4.2 contains the values for the timings for each of the Ultra DMA Mode

5.6 TimingC141-E050-02EN 5-1015.6.4.5 Device terminating an Ultra DMA data in burst5.6.4.2 contains the values for the timings for each of the Ultra

Interface5-102 C141-E050-02EN5.6.4.6 Host terminating an Ultra DMA data in burst5.6.4.2 contains the values for the timings for each of the Ultra DMA

5.6 TimingC141-E050-02EN 5-1035.6.4.7 Initiating an Ultra DMA data out burst5.6.4.2 contains the values for the timings for each of the Ultra DMA Mod

Interface5-104 C141-E050-02EN5.6.4.8 Sustained Ultra DMA data out burst5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes.Not

5.6 TimingC141-E050-02EN 5-1055.6.4.9 Device pausing an Ultra DMA data out burst5.6.4.2 contains the values for the timings for each of the Ultra DMA

Interface5-106 C141-E050-02EN5.6.4.10 Host terminating an Ultra DMA data out burst5.6.4.2 contains the values for the timings for each of the Ultra DM

5.6 TimingC141-E050-02EN 5-1075.6.4.11 Device terminating an Ultra DMA data in burst5.6.4.2 contains the values for the timings for each of the Ultra

Interface5-108 C141-E050-02EN5.6.5 Power-on and resetFigure 5.11 shows power-on and reset (hardware and software reset) timing.(1) Only master device

ContentsC141-E050-02EN xiiiFigure 5.5 WRITE SECTOR(S) command protocol 5-73Figure 5.6 Protocol for the command execution without data transfer

C141-E050-02EN 6-1CHAPTER 6 Operations6.1 Device Response to the Reset6.2 Address Translation6.3 Power Save6.4 Defect Management6.5 Read-Ahead Cache6.

Operations6-2 C141-E050-02EN6.1 Device Response to the ResetThis section describes how the PDIAG- and DASP- signals responds when thepower of the IDD

6.1 Device Response to the ResetC141-E050-02EN 6-3Figure 6.1 Response to power-on31 sec.30 sec.

Operations6-4 C141-E050-02EN6.1.2 Response to hardware resetResponse to RESET- (hardware reset through the interface) is similar to thepower-on reset.

6.1 Device Response to the ResetC141-E050-02EN 6-56.1.3 Response to software resetThe master device does not check the DASP- signal for a software re

Operations6-6 C141-E050-02EN6.1.4 Response to diagnostic commandWhen the master device receives an EXECUTE DEVICE DIAGNOSTICcommand and the slave devi

6.2 Address TranslationC141-E050-02EN 6-76.2 Address TranslationWhen the IDD receives any command which involves access to the disk medium,the IDD al

Operations6-8 C141-E050-02EN6.2.2 Logical address(1) CHS modeLogical address assignment starts from physical cylinder (PC) 0, physical head(PH) 0, and

6.3 Power SaveC141-E050-02EN 6-9(2) LBA modeLogical address assignment in the LBA mode starts from physical cylinder 0,physical head 0, and physical

Operations6-10 C141-E050-02EN• Standby mode• Sleep modeThe drive moves from the Active mode to the idle mode by itself.Regardless of whether the power

Contentsxiv C141-E050-02ENTable 3.1 Surface temperature measurement points and standard values3-6Table 3.2 Cable connector specifications 3-9Table

6.4 Defect ManagementC141-E050-02EN 6-11When one of following commands is issued, the command is executed normallyand the device is still stayed in t

Operations6-12 C141-E050-02EN6.4.1 Spare areaFollowing two types of spare area are provided for every physical head.1) Spare cylinder for sector slip:

6.4 Defect ManagementC141-E050-02EN 6-13(2) Alternate cylinder assignmentA defective sector is assigned to the spare sector in the alternate cylinder

Operations6-14 C141-E050-02EN6.5 Read-Ahead CacheAfter read command which involes read data from the disk medium is completed,the read-ahead cache fun

6.5 Read-Ahead CacheC141-E050-02EN 6-15• READ SECTOR (S)• READ MULTIPLE• READ DMAWhen caching operation is disabled by the SET FEATURES command, nocac

Operations6-16 C141-E050-02EN− READ MULTIPLE− WRITE SECTOR(S)− WRITE MULTIPLE− WRITE VERIFY SECTOR(S)3) Caching operation is inhibited by the SET FEAT

6.5 Read-Ahead CacheC141-E050-02EN 6-172) Transfers the requested data that already read to the host system with readingthe requested data from the di

Operations6-18 C141-E050-02EN1) At receiving the sequential read command, the disk drive sets the DAP andHAP to the start address of the segment and r

6.5 Read-Ahead CacheC141-E050-02EN 6-19b. Sequential hitWhen the previously executed read command is the sequential commandand the last sector address

Operations6-20 C141-E050-02EN4) Finally, the cache data in the buffer is as follows.Read-ahead datac. Non-sequential command immediately after sequent

C141-E050-02ENFOR SAFE OPERATIONHandling of This ManualThis manual contains important information for using this product. Read thoroughly before usin

C141-E050-02EN 1-1CHAPTER 1 Device Overview1.1 Features1.2 Device Specifications1.3 Power Requirements1.4 Environmental Specifications1.5 Acoustic Noi

6.5 Read-Ahead CacheC141-E050-02EN 6-213) The cache data for next read command is as follows.Cache data6.5.3.4 Partially hitA part of requested data i

Operations6-22 C141-E050-02EN3) The cache data for next read command is as follows.Cache data6.6 Write CacheThe write cache function of the drive make

6.6 Write CacheC141-E050-02EN 6-23The drive uses a cache data of the last write command as a read cache data. Whena read command is issued to the sa

C141-E050-02EN GL-1GlossaryActuatorHead positioning assembly. The actuator consists of a voice coil motor and headarm. If positions the read-write (

GlossaryGL-2 C141-E050-02ENMTBFMean time between failures. The MTBF is calculated by dividing the totaloperation time (total power-on time) by the nu

GlossaryC141-E050-02EN GL-3StatusThe status is a piece of one-byte information posted from the drive to the hostwhen command execution is ended. The

C141-E050-02EN AB-1Acronyms and AbbreviationsAABRT Abored commandAIC Automatic idle controlAMNF Address mark not foundATA AT attachmentAWG American wi

Device Overview1-2 C141-E050-02EN1.1 Features1.1.1 Functions and performanceThe fillowing features of the MHC Series and MHD Series are described.(1)

C141-E050-02EN IN-1Index1-drive connection 2-42-drive connection 2-58/8 GCR 4-108/9 GCR decoder 4-13AAcceleration mode 4-21Acoustic noise

IndexIN-2 C141-E050-02ENCommand, without data transfer 5-73Command block register 5-8Command code 5-14, 5-67Command description 5-16Command pr

IndexC141-E050-02EN IN-3Error posting 5-67Error rate 1-9Error register 5-8EXECUTE DEVICE DIAGNOSTIC 5-42Execution example of READ MULTIPLEcomm

IndexIN-4 C141-E050-02ENMode, acceleration 4-21Mode, active 6-10Mode, CHS 6-8Mode, idle 6-10Mode, LBA 6-9Mode, power save 1-2, 6-9Mode, sl

IndexC141-E050-02EN IN-5RECALIBRATE 5-28Recovery, write/read 4-19Register, command block 5-8Register, control block 5-13Register, I/O 5-6Rel

IndexIN-6 C141-E050-02ENTTemperature, ambient 3-5Temperature, range 1-2Temperature measurement point, surface3-5Temperature range 1-2Theory of d

C141-E050-01ENComment FormWe would appreciate your comments and suggestions regarding this manual.Manual codeC141-E050-02ENManual nameMHC2032AT, MHC20

MHC2032/2040AT, MHD2032/2021AT DISK DRIVES PRODUCT MANUALC141-E050-02ENMHC2032/2040AT, MHD2032/2021AT DISK DRIVES PRODUCT MANUALC141-E050-02EN

1.1 FeaturesC141-E050-02EN 1-31.1.3 Interface(1) Connection to interfaceWith the built-in ATA interface controller, the disk drives (the MHC Series a

Device Overview1-4 C141-E050-02EN1.2 Device Specifications1.2.1 Specifications summaryTable 1.1 shows the specfications of the disk drives (MHC2032AT/

1.2 Device SpecificationsC141-E050-02EN 1-5Table 1.2 shows the specfications of the disk drives (MHD2021AT/MHD2032AT).Table 1.2 Specifications (MHD20

Device Overview1-6 C141-E050-02ENModelFormatted CapacityNo. of CylinderNo. of HeadsNo. of SectorsMHC2032AT3,253.46 MB6,30416 63MHC2040AT4,099.86 MB7,9

1.3 Power RequirementsC141-E050-02EN 1-7(3) Current Requirements and Power DissipationTable 1.4 lists the current and power dissipation.Table 1.4 Cur

Device Overview1-8 C141-E050-02EN(5) Power on/off sequenceThe voltage detector circuits (the MHC Series and MHD Series) monitor +5 V.The circuits do n

1.7 ReliabilityC141-E050-02EN 1-91.6 Shock and VibrationTable 1.7 lists the shock and vibration specification.Table 1.7 Shock and vibration specifica

Device Overview1-10 C141-E050-02EN(3) Service lifeIn situations where management and handling are correct, the disk drive requiresno overhaul for five

C141-E050-02EN 2-1CHAPTER 2 Device Configuration2.1 Device Configuration2.2 System ConfigurationThis chapter describes the internal configurations of

Device Configuration2-2 C141-E050-02EN2.1 Device ConfigurationFigure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE),read/

2.1 Device ConfigurationC141-E050-02EN 2-3045HeadMHC2040AT2130HeadMHC2032AT2130HeadMHD2032AT3120HeadMHD2021AT12Figure 2.2 Configuration of disk media

Device Configuration2-4 C141-E050-02EN(5) Air circulation systemThe disk enclosure (DE) is sealed to prevent dust and dirt from entering. The diskenc

2.2 System ConfigurationC141-E050-02EN 2-52.2.3 2 drives connectionMHC2032ATMHC2040ATMHC2032ATMHC2040AT(Host adaptor)Note:When the drive that is not

C141-E050-02EN 3-1CHAPTER 3 Installation Conditions3.1 Dimensions3.2 Mounting3.3 Cable Connections3.4 Jumper SettingsThis chapter gives the external d

Installation Conditions3-2 C141-E050-02EN3.1 DimensionsFigure 3.1 illustrates the dimensions of the disk drive and positions of themounting screw hole

3.2 MountingC141-E050-02EN 3-3Figure 3.1 Dimensions (MHD series) (2/2)

Installation Conditions3-4 C141-E050-02EN3.2 Mounting(1) OrientationFigure 3.2 illustrates the allowable orientations for the disk drive.

C141-E050-02ENRevision History(1/1)Edition Date Revised section (*1)(Added/Deleted/Altered)Details01 1998-02-15 — —02 1998-0-*1 Section(s) with asteri

3.2 MountingC141-E050-02EN 3-5(2) FrameThe MR head bias of the HDD disk enclosure (DE) is zero. The mounting frameis connected to SG.Use M3 screw fo

Installation Conditions3-6 C141-E050-02EN(4) Ambient temperatureThe temperature conditions for a disk drive mounted in a cabinet refer to theambient t

3.2 MountingC141-E050-02EN 3-7(5) Service areaFigure 3.5 shows how the drive must be accessed (service areas) during and afterinstallation.Figure 3.5

Installation Conditions3-8 C141-E050-02EN3.3 Cable Connections3.3.1 Device connectorThe disk drive has the connectors and terminals listed below for c

3.3 Cable ConnectionsC141-E050-02EN 3-93.3.2 Cable connector specificationsTable 3.2 lists the recommended specifications for the cable connectors.Ta

Installation Conditions3-10 C141-E050-02EN3.3.4 Power supply connector (CN1)Figure 3.8 shows the pin assignment of the power supply connector (CN1).Fi

3.4 Jumper SettingsC141-E050-02EN 3-113.4.2 Factory default settingFigure 3.10 shows the default setting position at the factory.Figure 3.10 Factory

Installation Conditions3-12 C141-E050-02EN3.4.4 CSEL settingFigure 3.12 shows the cable select (CSEL) setting.Note:The CSEL setting is not depended on

3.4 Jumper SettingsC141-E050-02EN 3-13Figure 3.14 Example (2) of Cable Select

C141-E050-02EN 4-1CHAPTER 4 Theory of Device Operation4.1 Outline4.2 Subassemblies4.3 Circuit Configuration4.4 Power-on Sequence4.5 Self-calibration4.

Theory of Device Operation4-2 C141-E050-02EN4.1 OutlineThis chapter consists of two parts. First part (Section 4.2) explains mechanicalassemblies of

4.2 SubassembliesC141-E050-02EN 4-3045HeadMHC2040AT2130HeadMHC2032AT2130HeadMHD2032AT3120HeadMHD2021AT12Figure 4.1 Head structure4.2.3 SpindleThe spi

Theory of Device Operation4-4 C141-E050-02EN4.3 Circuit ConfigurationFigure 4.2 shows the disk drive circuit configuration.(1) Read/write circuitThe r

4.3 Circuit ConfigurationC141-E050-02EN 4-5Figure 4.2 Circuit Configuration

Theory of Device Operation4-6 C141-E050-02EN4.4 Power-on SequenceFigure 4.3 describes the operation sequence of the disk drive at power-on. Theoutlin

4.5 Self-calibrationC141-E050-02EN 4-7Figure 4.3 Power-on operation sequence4.5 Self-calibrationThe disk drive occasionally performs self-calibration

Theory of Device Operation4-8 C141-E050-02ENThe forces are compensated by adding the measured value to the specified currentvalue to the power amplifi

4.6 Read/write CircuitC141-E050-02EN 4-9Table 4.1 Self-calibration execution timechartTime elapsedTime elapsed(accumulated)1At power-onInitial calibr

Theory of Device Operation4-10 C141-E050-02ENsignal (WUS) when a write error occurs due to head short-circuit or headdisconnection.The Pre AMP sets th

C141-E050-02EN iPrefaceThis manual describes the MHC Series and MHD Series, 2.5-inch hard disk drives.These drives have a built-in controller that is

4.6 Read/write CircuitC141-E050-02EN 4-11Figure 4.4 Read/write circuit block diagram

Theory of Device Operation4-12 C141-E050-02EN4.6.3 Read circuitThe head read signal from the PreAMP is regulated by the automatic gain control(AGC) ci

4.6 Read/write CircuitC141-E050-02EN 4-13(3) Flash digitizer circuitThis circuit is 10-tap sampled analog transversal filter circuit that cosine-equa

Theory of Device Operation4-14 C141-E050-02EN4.7 Servo ControlThe actuator motor and the spindle motor are submitted to servo control. Theactuator mo

4.7 Servo ControlC141-E050-02EN 4-15The major internal operations are listed below.a. Spindle motor startStarts the spindle motor and accelerates it

Theory of Device Operation4-16 C141-E050-02ENFigure 4.7 Physical sector servo configuration on disk surfaceServo frame(60 servo framesrevolution)Circu

4.7 Servo ControlC141-E050-02EN 4-17(2) Servo burst capture circuitThe servo burst capture circuit reproduces signals (position signals) that indicat

Theory of Device Operation4-18 C141-E050-02EN4.7.2 Data-surface servo formatFigure 4.7 describes the physical layout of the servo frame. The three ar

4.7 Servo ControlC141-E050-02EN 4-19(1) Write/read recoveryThis area is used to absorb the write/read transient and to stabilize the AGC.(2) Servo ma

Theory of Device Operation4-20 C141-E050-02ENd) If the head is stopped at the reference cylinder from there. Track followingcontrol starts.(2) Seek o

Prefaceii C141-E050-02ENConventions for Alert MessagesThis manual uses the following conventions to show the alert messages. An alertmessage consists

4.7 Servo ControlC141-E050-02EN 4-21d) During phase switching, the spindle motor starts rotating in low speed, andgenerates a counter electromotive f

C141-E050-02EN 5-1CHAPTER 5 Interface5.1 Physical Interface5.2 Logical Interface5.3 Host Commands5.4 Command Protocol5.5 Ultra DMA Feature Set5.6 Timi

Interface5-2 C141-E050-02EN5.1 Physical Interface5.1.1 Interface signalsFigure 5.1 shows the interface signals.INTRQ: INTERRUPT REQUESTIOCS16-: 16-BIT

5.1 Physical InterfaceC141-E050-02EN 5-35.1.2 Signal assignment on the connectorTable 5.1 shows the signal assignment on the interface connector.Tabl

Interface5-4 C141-E050-02EN[signal][I/O][Description]ENCSELIThis signal is used to set master/slave using the CSEL signal (pin 28).Pins A and C Open:

5.1 Physical InterfaceC141-E050-02EN 5-5[signal][I/O][Description]IOCS16-OThis signal indicates 16-bit data bus is addressed in PIO data transfer.Thi

Interface5-6 C141-E050-02EN[signal][I/O][Description]DMARQOThis signal is used for DMA transfer between the host system andthe device. The device ass

5.2 Logical InterfaceC141-E050-02EN 5-75.2.1 I/O registersCommunication between the host system and the device is done through input-output (I/O) reg

Interface5-8 C141-E050-02EN5.2.2 Command block registers(1) Data register (X’1F0’)The Data register is a 16-bit register for data block transfer betwe

PrefaceC141-E050-02EN iiiLiability Exception“Disk drive defects” refers to defects that involve adjustment, repair, orreplacement.Fujitsu is not liabl

5.2 Logical InterfaceC141-E050-02EN 5-9[Diagnostic code]X’01’:No Error Detected.X’02’:HDC Register Compare ErrorX’03’:Data Buffer Compare Error.X’05’

Interface5-10 C141-E050-02EN(6) Cylinder Low register (X’1F4’)The contents of this register indicates low-order 8 bits of the starting cylinderaddress

5.2 Logical InterfaceC141-E050-02EN 5-11(9) Status register (X’1F7’)The contents of this register indicate the status of the device. The contents of

Interface5-12 C141-E050-02EN- Bit 5:The Device Write Fault (DF) bit. This bit indicates that a device fault(write fault) condition has been detected.

5.3 Host CommandsC141-E050-02EN 5-135.2.3 Control block registers(1) Alternate Status register (X’3F6’)The Alternate Status register contains the sam

Interface5-14 C141-E050-02ENWhen the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the datatransfer) and the host system writes to the co

5.3 Host CommandsC141-E050-02EN 5-15Table 5.3 Command code and parameters (2 of 2)Command code (Bit)Parameters used7 6 5 4 3 2 1 0 FR SC SN CY DHIDLE

Interface5-16 C141-E050-02ENY*: Necessary to set parameters under the LBA mode.N: Not necessary to set parameters (The parameter is ignored if it is s

5.3 Host CommandsC141-E050-02EN 5-17CM: Command register FR: Features registerDH: Device/Head register ST: Status registerCH: Cylinder High regi

Interface5-18 C141-E050-02ENCommand block registers contain the cylinder, the head, and the sector addressesof the sector (in the CHS mode) or the log

5.3 Host CommandsC141-E050-02EN 5-19The implementation of the READ MULTIPLE command is identical to that of theREAD SECTOR(S) command except that the

Interface5-20 C141-E050-02ENFigure 5.2 Execution example of READ MULTIPLE commandAt command issuance (I/O registers setting contents)1F7H(CM)1 1 0 0 0

5.3 Host CommandsC141-E050-02EN 5-21(3) READ DMA (X’C8’ or X’C9’)This command operates similarly to the READ SECTOR(S) command except forfollowing ev

Interface5-22 C141-E050-02ENAt command completion (I/O registers contents to be read)1F7H(ST)Status information1F6H(DH)×L×DVEnd head No. /LBA [MSB]1F5

5.3 Host CommandsC141-E050-02EN 5-23At command issuance (I/O registers setting contents)1F7H(CM)0 1 0 0 0 0 0 R1F6H(DH)×L×DVStart head No. /LBA [MSB]

Interface5-24 C141-E050-02ENThe data stored in the buffer, and CRC code and ECC bytes are written to the datafield of the corresponding sector(s). Upo

5.3 Host CommandsC141-E050-02EN 5-25(6) WRITE MULTIPLE (X’C5’)This command is similar to the WRITE SECTOR(S) command. The device doesnot generate int

Interface5-26 C141-E050-02ENAt command issuance (I/O registers setting contents)1F7H(CM)1 1 0 0 0 1 0 11F6H(DH)×L×DVStart head No. /LBA [MSB]1F5H(CH)1

5.3 Host CommandsC141-E050-02EN 5-27A host system can select the following transfer mode using the SET FEATUREScommand.1) Single word DMA transfer mo

Interface5-28 C141-E050-02ENAfter all sectors are verified, the last interruption (INTRQ for commandtermination) is generated.At command issuance (I/O