Fujitsu MHA2032AT Bedienungsanleitung

C141-E042-01ENMHA2021AT, MHA2032ATDISK DRIVESPRODUCT MANUAL

ContentsC141-E042-01EN ix4.6.3 Read circuit 4-124.6.4 Time base generator circuit 4-134.7 Servo Control 4-144.7.1 Servo control circuit

5.3 Host CommandsC141-E042-01EN 5-39At command issuance (I/O registers setting contents)1F7H(CM) 111011111F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H

Interface5-40 C141-E042-01ENSingle word DMA transfer mode X 00001 000 (X’10’: Mode 0)00010 001 (X’11’: Mode 1)00010 010 (X’12’: Mode 2)Multiword

5.3 Host CommandsC141-E042-01EN 5-41At command issuance (I/O registers setting contents)1F7H(CM) 110001101F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H

Interface5-42 C141-E042-01ENWord 47Bit 7-0 = 20:Word 59 = 0000:= 01xx:Maximum number of sectors that can be transferred per interruptby the READ MULTI

5.3 Host CommandsC141-E042-01EN 5-43Table 5.6 Diagnostic codeCode Result of diagnosticX’01’X’03’X’05’X’8x’No error detected.Data buffer compare error

Interface5-44 C141-E042-01ENcommand is used for checking ECC function by combining with the WRITELONG command.Number of ECC bytes to be transferred is

5.3 Host CommandsC141-E042-01EN 5-45This command is operated under the following conditions:• The command is issued in a sequence of the READ LONG or

Interface5-46 C141-E042-01ENAt command issuance (I/O registers setting contents)1F7H(CM) 111101001F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H(

5.3 Host CommandsC141-E042-01EN 5-47At command issuance (I/O registers setting contents)1F7H(CM) 111110001F6H(DH)××´DVxx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(

Interface5-48 C141-E042-01ENSector Count register value Point of timer0 [X’00’] 30 minutes1 to 3 [X’01’ to X’03’] 15 seconds4 to 240 [X’04’ to X’F0’](

Contentsx C141-E042-01ENCHAPTER 6 Operations...6-16.1 Device Response t

5.3 Host CommandsC141-E042-01EN 5-49(22) IDLE IMMEDIATE (X’95’ or X’E1’)Upon receipt of this command, the device sets the BSY bit of the Status regi

Interface5-50 C141-E042-01ENUnder the standby mode, the spindle motor is stopped. Thus, when the commandinvolving a seek such as the READ SECTOR(s) c

5.3 Host CommandsC141-E042-01EN 5-51At command issuance (I/O registers setting contents)1F7H(CM) X’94’ or X’E0’1F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(S

Interface5-52 C141-E042-01ENAt command issuance (I/O registers setting contents)1F7H(CM) X’99’ or X’E6’1F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC

5.3 Host CommandsC141-E042-01EN 5-53At command issuance (I/O registers setting contents)1F7H(CM) X’98’ or X’E5’1F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(S

Interface5-54 C141-E042-01ENTable 5.7 Features Register values (subcommands) and functionsFeatures Resister FunctionX’D0’ SMART Read Attribute Values:

5.3 Host CommandsC141-E042-01EN 5-55Features Resister FunctionX’DA’ SMART Return Status:When the device receives this subcommand, it asserts the BSY

Interface5-56 C141-E042-01ENAt command completion (I-O registers setting contents)1F7H(ST) Status information1F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1

5.3 Host CommandsC141-E042-01EN 5-57Table 5.9 Format of insurance failure threshold value dataByte Item0001Data format version number02 Attribute 1 A

Interface5-58 C141-E042-01ENAttributeIDAttribute name10 Number of retries made to activate the spindle motor12 Number of power-on-power-off times13 to

ContentsC141-E042-01EN xiIllustrationsFiguresFigure 1.1 Current fluctuation (Typ.) at +5V when power is turned on 1-6Figure 2.1 Disk drive outervi

5.3 Host CommandsC141-E042-01EN 5-59The limit of a varying attribute value. The host compares the attribute valueswith the thresholds to identify a

Interface5-60 C141-E042-01ENAt command issuance (I-O register contents))1F7H(CM) 111101101F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H(FR)xxxxx

5.3 Host CommandsC141-E042-01EN 5-61At command issuance (I-O register contents)1F7H(CM) 111100111F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H(

Interface5-62 C141-E042-01ENAt command issuance (I-O register contents)1F7H(CM) 111101001F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H(FR)xxxxxx

5.3 Host CommandsC141-E042-01EN 5-63• READ DMA • WRITE DMA • SECURITY DISABLE PASSWORD• READ LONG • WRITE LONG • SECURITY FREEZE LOCK• READ MU

Interface5-64 C141-E042-01EN(32) SECURITY SET PASSWORD (F1h)This command enables a user password or master password to be set.The host transfers the

5.3 Host CommandsC141-E042-01EN 5-65Table 5.12 Relationship between combination of Identifier and Security level, andoperation of the lock functionIn

Interface5-66 C141-E042-01EN(33) SECURITY UNLOCK (F2h)This command cancels LOCKED MODE.The host transfers the 512-byte data shown in Table 1.1 to the

5.3 Host CommandsC141-E042-01EN 5-67At command completion (I-O register contents)1F7H(CM) Status information1F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1

Interface5-68 C141-E042-01ENTable 5.13 Command code and parameters (2 of 2)Command name Error register (X’1F1’) Status register (X’1F7’)BBK UNC INDF A

Contentsxii C141-E042-01ENFigure 5.6 Protocol for the command execution without data transfer 5-73Figure 5.7 Normal DMA data transfer 5-75Figu

5.4 Command ProtocolC141-E042-01EN 5-695.4 Command ProtocolThe host should confirm that the BSY bit of the Status register of the device is 0prior to

Interface5-70 C141-E042-01ENwords, the host should receive the relevant sector of data (512 bytes of uninsureddummy data) or release the DRQ status by

5.4 Command ProtocolC141-E042-01EN 5-71last sector in multiple-sector reading. If the timing to read the Status register does not meetabove conditio

Interface5-72 C141-E042-01ENb) The host writes a command code in the Command register. The drive sets theBSY bit of the Status register.c) When the de

5.4 Command ProtocolC141-E042-01EN 5-73Note:For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order toclear INTRQ

Interface5-74 C141-E042-01EN5.4.4 Other commands• READ MULTIPLE• SLEEP• WRITE MULTIPLESee the description of each command.5.4.5 DMA data transfer comm

5.4 Command ProtocolC141-E042-01EN 5-75Figure 5.7 Normal DMA data transfer

Interface5-76 C141-E042-01EN5.5 Timing5.5.1 PIO data transferFigure 5.8 shows of the data transfer timing between the device and the hostsystem.

5.5 TimingC141-E042-01EN 5-77Figure 5.8 Data transfer timing

Interface5-78 C141-E042-01EN5.5.2 Single word DMA data transferFigure 5.9 show the single word DMA data transfer timing between the deviceand the host

ContentsC141-E042-01EN xiiiTable 5.10 Contents of security password 5-59Table 5.11 Contents of SECURITY SET PASSWORD data 5-64Table 5.12 Relat

5.5 TimingC141-E042-01EN 5-795.5.3 Multiword DMA data transferFigure 5.10 shows the multiword DMA data transfer timing between the deviceand the host

Interface5-80 C141-E042-01EN(2) Master and slave devices are present (2-drives configulation)Figure 5.11 Power on Reset Timing

C141-E042-01EN 6-1CHAPTER 6 Operations6.1 Device Response to the Reset6.2 Address Translation6.3 Power Save6.4 Defect Management6.5 Read-Ahead Cache6.

Operations6-2 C141-E042-01EN6.1 Device Response to the ResetThis section describes how the PDIAG- and DASP- signals responds when thepower of the IDD

6.1 Device Response to the ResetC141-E042-01EN 6-3Figure 6.1 Response to power-on

Operations6-4 C141-E042-01EN6.1.2 Response to hardware resetResponse to RESET- (hardware reset through the interface) is similar to thepower-on reset.

6.1 Device Response to the ResetC141-E042-01EN 6-56.1.3 Response to software resetThe master device does not check the DASP- signal for a software re

Operations6-6 C141-E042-01EN6.1.4 Response to diagnostic commandWhen the master device receives an EXECUTE DEVICE DIAGNOSTICcommand and the slave devi

6.2 Address TranslationC141-E042-01EN 6-76.2 Address TranslationWhen the IDD receives any command which involves access to the disk medium,the IDD al

Operations6-8 C141-E042-01EN6.2.2 Logical address(1) CHS modeLogical address assignment starts from physical cylinder (PC) 0, physical head(PH) 0, and

C141-E042-01EN 1-1CHAPTER 1 Device Overview1.1 Features1.2 Device Specifications1.3 Power Requirements1.4 Environment Specifications1.5 Acoustic Noise

6.3 Power SaveC141-E042-01EN 6-9(2) LBA modeLogical address assignment in the LBA mode starts from physical cylinder 0,physical head 0, and physical

Operations6-10 C141-E042-01EN• Standby mode• Sleep modeThe drive moves from the Active mode to the idle mode by itself.Regardless of whether the power

6.4 Defect ManagementC141-E042-01EN 6-11When one of following commands is issued, the command is executed normallyand the device is still stayed in t

Operations6-12 C141-E042-01EN6.4.1 Spare areaFollowing two types of spare area are provided for every physical head.1) Spare cylinder for sector slip:

6.4 Defect ManagementC141-E042-01EN 6-13(2) Alternate cylinder assignmentA defective sector is assigned to the spare sector in the alternate cylinder

Operations6-14 C141-E042-01EN6.5 Read-Ahead CacheAfter read command which involes read data from the disk medium is completed,the read-ahead cache fun

6.5 Read-Ahead CacheC141-E042-01EN 6-15• READ SECTOR (S)• READ MULTIPLE• READ DMAWhen caching operation is disabled by the SET FEATURES command, noca

Operations6-16 C141-E042-01EN− READ MULTIPLE− WRITE SECTOR(S)− WRITE MULTIPLE− WRITE VERIFY SECTOR(S)3) Caching operation is inhibited by the SET

6.5 Read-Ahead CacheC141-E042-01EN 6-172) Transfers the requested data that already read to the host system with readingthe requested data from the d

Operations6-18 C141-E042-01EN1) At receiving the sequential read command, the disk drive sets the DAP andHAP to the start address of the segment and r

Device Overview1-2 C141-E042-01EN1.1 Features1.1.1 Functions and performance(1) CompactThe disk has 1 or 2 disks of 65 mm (2.5 inches) diameter, and i

6.5 Read-Ahead CacheC141-E042-01EN 6-19b. Sequential hitWhen the previously executed read command is the sequential commandand the last sector addres

Operations6-20 C141-E042-01EN4) Finally, the cache data in the buffer is as follows.Read-ahead data(3) Full hit (hit all)All requested data are stored

6.5 Read-Ahead CacheC141-E042-01EN 6-21(4) Partially hitA part of requested data including a lead sector are stored in the data buffer. Thedisk driv

Operations6-22 C141-E042-01EN6.6 Write CacheThe write cache function of the drive makes a high speed processing in the casethat data to be written by

6.6 Write CacheC141-E042-01EN 6-23• WRITE SECTOR(S) WITH RETRY• WRITE MULTIPLE• WRITE DMA WITH RETRY

C141-E042-01EN GL-1GlossaryActuatorHead positioning assembly. The actuator consists of a voice coil motor and headarm. If positions the read-write (

GlossaryGL-2 C141-E042-01ENMTBFMean time between failures. The MTBF is calculated by dividing the totaloperation time (total power-on time) by the nu

GlossaryC141-E042-01EN GL-3StatusThe status is a piece of one-byte information posted from the drive to the hostwhen command execution is ended. The

C141-E042-01EN AB-1Acronyms and AbbreviationsAABRT Abored commandAIC Automatic idle controlAMNF Address mark not foundATA AT attachmentAWG American wi

C141-E042-01EN IN-1Index1-drive connection 2-42-drive connection 2-58/8 GCR 4-108/9 GCR decoder 4-13AAcceleration mode 4-21Acoustic noise

1.1 FeaturesC141-E042-01EN 1-3(2) 128-KB data bufferThe disk drive uses a 128-KB data buffer to transfer data between the host and thedisk media.In c

IndexIN-2 C141-E042-01ENCommand, sequential 6-17Command, without data transfer 5-73Command block register 5-8Command code 5-14, 5-67Command de

IndexC141-E042-01EN IN-3Error correction by retry 1-3Error posting 5-67Error rate 1-9Error register 5-8EXECUTE DEVICE DIAGNOSTIC 5-42Executi

IndexIN-4 C141-E042-01ENMis-hit 6-16Mode, acceleration 4-21Mode, active 6-10Mode, CHS 6-8Mode, idle 6-10Mode, LBA 6-9Mode, power save 1-

IndexC141-E042-01EN IN-5Read/write preamplifier 4-9RECALIBRATE 5-28Recovery, write/read 4-19Register, command block 5-8Register, control block

IndexIN-6 C141-E042-01ENSurface temperature measurement point3-5System configuration 2-4TTemperature, ambient 3-5Temperature, range 1-2Temperatu

C141-E042-01ENComment FormWe would appreciate your comments and suggestions regarding this manual.Manual code C141-E042-01ENManual name MHA2021AT, MHA

MHA2021AT, MHA2032AT DISK DRIVES PRODUCT MANUALC141-E042-01ENMHA2021AT, MHA2032AT DISK DRIVES PRODUCT MANUALC141-E042-01EN

Device Overview1-4 C141-E042-01EN1.2 Device Specifications1.2.1 Specifications summaryTable 1.1 shows the specfications of the disk drive.Table 1.1 Sp

1.3 Power RequirementsC141-E042-01EN 1-5*1: Capacity under the LBA mode.Under the CHS mode (normal BIOS specification), formatted capacity,number of

C141-E042-01ENFOR SAFE OPERATIONHandling of This ManualThis manual contains important information for using this product. Read thoroughly before usin

Device Overview1-6 C141-E042-01EN(3) Current Requirements and Power DissipationTable 1.3 lists the current and power dissipation.Table 1.3 Current and

1.5 Acoustic NoiseC141-E042-01EN 1-71.4 Environmental SpecificationsTable 1.4 lists the environmental specifications.Table 1.4 Environmental specific

Device Overview1-8 C141-E042-01EN1.6 Shock and VibrationTable 1.6 lists the shock and vibration specification.Table 1.6 Shock and vibration specificat

1.9 Media DefectsC141-E042-01EN 1-9(3) Service lifeIn situations where management and handling are correct, the disk drive requiresno overhaul for fi

C141-E042-01EN 2-1CHAPTER 2 Device Configuration2.1 Device Configuration2.2 System ConfigurationThis chapter describes the internal configurations of

Device Configuration2-2 C141-E042-01EN2.1 Device ConfigurationFigure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE),read/

2.1 Device ConfigurationC141-E042-01EN 2-3MHA2021AT0123HeadMHA2032AT0123Head45Figure 2.2 Configuration of disk media heads(3) Spindle motorThe disks

Device Configuration2-4 C141-E042-01EN(5) Air circulation systemThe disk enclosure (DE) is sealed to prevent dust and dirt from entering. The diskenc

2.2 System ConfigurationC141-E042-01EN 2-52.2.3 2 drives connectionMHA2021ATMHA2032ATMHA2021ATMHA2032AT(Host adaptor)Note:When the drive that is not

C141-E042-01EN 3-1CHAPTER 3 Installation Conditions3.1 Dimensions3.2 Mounting3.3 Cable Connections3.4 Jumper SettingsThis chapter gives the external d

C141-E042-01ENRevision History(1/1)Edition Date Revised section (*1)(Added/Deleted/Altered)Details01 1997-07-15 — —*1 Section(s) with asterisk (*) ref

Installation Conditions3-2 C141-E042-01EN3.1 DimensionsFigure 3.1 illustrates the dimensions of the disk drive and positions of themounting screw hole

3.2 MountingC141-E042-01EN 3-33.2 Mounting(1) OrientationFigure 3.2 illustrates the allowable orientations for the disk drive.Figure 3.2 Orientation(

Installation Conditions3-4 C141-E042-01EN(2) FrameThe MR head bias of the HDD disk enclosure (DE) is zero. The mounting frameis connected to SG.Use M

3.2 MountingC141-E042-01EN 3-5(4) Ambient temperatureThe temperature conditions for a disk drive mounted in a cabinet refer to theambient temperature

Installation Conditions3-6 C141-E042-01EN(5) Service areaFigure 3.5 shows how the drive must be accessed (service areas) during and afterinstallation.

3.3 Cable ConnectionsC141-E042-01EN 3-73.3 Cable Connections3.3.1 Device connectorThe disk drive has the connectors and terminals listed below for co

Installation Conditions3-8 C141-E042-01EN3.3.2 Cable connector specificationsTable 3.2 lists the recommended specifications for the cable connectors.T

3.4 Jumper SettingsC141-E042-01EN 3-93.3.4 Power supply connector (CN1)Figure 3.8 shows the pin assignment of the power supply connector (CN1).Figure

Installation Conditions3-10 C141-E042-01EN3.4.2 Factory default settingFigure 3.10 shows the default setting position at the factory.Figure 3.10 Facto

3.4 Jumper SettingsC141-E042-01EN 3-113.4.4 CSEL settingFigure 3.12 shows the cable select (CSEL) setting.Note:The CSEL setting is not depended on se

C141-E042-01EN iPrefaceThis manual describes the MHA2021AT and MHA2032AT, 2.5-inch hard diskdrives. These drives have a built-in controller that is c

Installation Conditions3-12 C141-E042-01ENFigure 3.14 Example (2) of Cable Select

C141-E042-01EN 4-1CHAPTER 4 Theory of Device Operation4.1 Outline4.2 Subassemblies4.3 Circuit Configuration4.4 Power-on sequence4.5 Self-calibration4.

Theory of Device Operation4-2 C141-E042-01EN4.1 OutlineThis chapter consists of two parts. First part (Section 4.2) explains mechanicalassemblies of

4.2 SubassembliesC141-E042-01EN 4-3MHA2021AT0123HeadMHA2032AT0123Head45Figure 4.1 Head structure4.2.3 SpindleThe spindle consists of a disk stack ass

Theory of Device Operation4-4 C141-E042-01EN4.3 Circuit ConfigurationFigure 4.2 shows the disk drive circuit configuration.(1) Read/write circuitThe r

4.3 Circuit ConfigurationC141-E042-01EN 4-5Figure 4.2 Circuit Configuration

Theory of Device Operation4-6 C141-E042-01EN4.4 Power-on SequenceFigure 4.3 describes the operation sequence of the disk drive at power-on. Theoutlin

4.5 Self-calibrationC141-E042-01EN 4-7Figure 4.3 Power-on operation sequence4.5 Self-calibrationThe disk drive occasionally performs self-calibration

Theory of Device Operation4-8 C141-E042-01ENThe forces are compensated by adding the measured value to the specified currentvalue to the power amplifi

4.6 Read/write CircuitC141-E042-01EN 4-9Table 4.1 Self-calibration execution timechartTime elapsed Time elapsed(accumulated)1 At power-on Initial cal

Prefaceii C141-E042-01ENAbbreviationThis section gives the meanings of the definitions used in this manual.Conventions for Alert MessagesThis manual u

Theory of Device Operation4-10 C141-E042-01ENsignal (WUS) when a write error occurs due to head short-circuit or headdisconnection.4.6.2 Write circuit

4.6 Read/write CircuitC141-E042-01EN 4-11Figure 4.4 Read/write circuit block diagram

Theory of Device Operation4-12 C141-E042-01EN4.6.3 Read circuitThe head read signal from the PreAMP is regulated by the automatic gain control(AGC) ci

4.6 Read/write CircuitC141-E042-01EN 4-13(4) Viterbi detection circuitThe sample hold waveform output from the adaptive equalizer circuit is sent tot

Theory of Device Operation4-14 C141-E042-01EN4.7 Servo ControlThe actuator motor and the spindle motor are submitted to servo control. Theactuator mo

4.7 Servo ControlC141-E042-01EN 4-15The major internal operations are listed below.a. Spindle motor startStarts the spindle motor and accelerates it

Theory of Device Operation4-16 C141-E042-01ENFigure 4.7 Physical sector servo configuration on disk surface

4.7 Servo ControlC141-E042-01EN 4-17(2) Servo burst capture circuitThe servo burst capture circuit reproduces signals (position signals) that indicat

Theory of Device Operation4-18 C141-E042-01EN4.7.2 Data-surface servo formatFigure 4.7 describes the physical layout of the servo frame. The three ar

4.7 Servo ControlC141-E042-01EN 4-19(1) Write/read recoveryThis area is used to absorb the write/read transient and to stabilize the AGC.(2) Servo ma

PrefaceC141-E042-01EN iiiTo make this manual easier for users to understand, opinions from readers areneeded. Please write your opinions or requests

Theory of Device Operation4-20 C141-E042-01ENd) If the head is stopped at the reference cylinder from there. Track followingcontrol starts.(2) Seek o

4.7 Servo ControlC141-E042-01EN 4-21d) During phase switching, the spindle motor starts rotating in low speed, andgenerates a counter electromotive f

C141-E042-01EN 5-1CHAPTER 5 Interface5.1 Physical Interface5.2 Logical Interface5.3 Host Commands5.4 Command Protocol5.5 TimingThis chapter gives deta

Interface5-2 C141-E042-01EN5.1 Physical Interface5.1.1 Interface signalsFigure 5.1 shows the interface signals.Figure 5.1 Interface signals5.1.2 Signa

5.1 Physical InterfaceC141-E042-01EN 5-3Table 5.1 Signal assignment on the interface connectorPin No. Signal Pin No. SignalACE13579111315171921232527

Interface5-4 C141-E042-01EN[signal] [I/O] [Description]MSTR I MSTR, I, Master/slave setting1: Master 0: SlaveRESET- I Reset signal from the host. T

5.1 Physical InterfaceC141-E042-01EN 5-5[signal] [I/O] [Description]PIDAG- I/O This signal is an input mode for the master device and an outputmode f

Interface5-6 C141-E042-01EN5.2 Logical InterfaceThe device can operate for command execution in either address-specified mode;cylinder-head-sector (CH

5.2 Logical InterfaceC141-E042-01EN 5-7Table 5.2 I/O registersI/O registersRead operation Write operationCommand block registersL H L L L Data Data X

Interface5-8 C141-E042-01EN5.2.2 Command block registers(1) Data register (X’1F0’)The Data register is a 16-bit register for data block transfer betwe

C141-E042-01EN vImportant Alert ItemsImportant Alert MessagesThe important alert messages in this manual are as follows:A hazardous situation could re

5.2 Logical InterfaceC141-E042-01EN 5-9[Diagnostic code]X’01’: No Error Detected.X’02’: HDC Register Compare ErrorX’03’: Data Buffer Compare Error.X’

Interface5-10 C141-E042-01EN(6) Cylinder Low register (X’1F4’)The contents of this register indicates low-order 8 bits of the starting cylinderaddress

5.2 Logical InterfaceC141-E042-01EN 5-11(9) Status register (X’1F7’)The contents of this register indicate the status of the device. The contents of

Interface5-12 C141-E042-01EN- Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault(write fault) condition has been detected

5.3 Host CommandsC141-E042-01EN 5-135.2.3 Control block registers(1) Alternate Status register (X’3F6’)The Alternate Status register contains the sam

Interface5-14 C141-E042-01ENWhen the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the datatransfer) and the host system writes to the co

5.3 Host CommandsC141-E042-01EN 5-15Table 5.3 Command code and parameters (2 of 2)Command code (Bit) Parameters used76543210FRSCSNCYDHIDLE IMMEDIATE

Interface5-16 C141-E042-01ENY*: Necessary to set parameters under the LBA mode.N: Not necessary to set parameters (The parameter is ignored if it is s

5.3 Host CommandsC141-E042-01EN 5-17CM: Command register FR: Features registerDH: Device/Head register ST: Status registerCH: Cylinder High regi

Interface5-18 C141-E042-01ENCommand block registers contain the cylinder, the head, and the sector addressesof the sector (in the CHS mode) or the log

C141-E042-01EN viiContentsCHAPTER 1 Device Overview ... 1-11.1 Features 1-21.1

5.3 Host CommandsC141-E042-01EN 5-19The implementation of the READ MULTIPLE command is identical to that of theREAD SECTOR(S) command except that the

Interface5-20 C141-E042-01ENFigure 5.2 Execution example of READ MULTIPLE commandAt command issuance (I/O registers setting contents)1F7H(CM) 11000100

5.3 Host CommandsC141-E042-01EN 5-21(3) READ DMA (X’C8’ or X’C9’)This command operates similarly to the READ SECTOR(S) command except forfollowing ev

Interface5-22 C141-E042-01ENAt command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)×L×DV End head No. /LBA[MSB]1F

5.3 Host CommandsC141-E042-01EN 5-23At command issuance (I/O registers setting contents)1F7H(CM) 0100000R1F6H(DH)×L×DV Start head No. /LBA[MSB]1F5H(C

Interface5-24 C141-E042-01ENThe data stored in the buffer, and CRC code and ECC bytes are written to the datafield of the corresponding sector(s). Upo

5.3 Host CommandsC141-E042-01EN 5-25(6) WRITE MULTIPLE (X’C5’)This command is similar to the WRITE SECTOR(S) command. The device doesnot generate int

Interface5-26 C141-E042-01ENAt command issuance (I/O registers setting contents)1F7H(CM) 110001011F6H(DH)×L×DV Start head No. /LBA[MSB]1F5H(CH)1F4H(CL

5.3 Host CommandsC141-E042-01EN 5-27A host system can select the following transfer mode using the SET FEATUREScommand.1) Single word DMA transfer mo

Interface5-28 C141-E042-01ENAfter all sectors are verified, the last interruption (INTRQ for commandtermination) is generated.At command issuance (I/O

Contentsviii C141-E042-01ENCHAPTER 3 Installation Conditions...3-13.1 Dimensions 3-23.2

5.3 Host CommandsC141-E042-01EN 5-29At command issuance (I/O registers setting contents)1F7H(CM) 0001xxxx1F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H

Interface5-30 C141-E042-01ENAt command issuance (I/O registers setting contents)1F7H(CM) 0111xxxx1F6H(DH)×L×DV Head No. /LBA [MSB]1F5H(CH)1F4H(CL)1F3H

5.3 Host CommandsC141-E042-01EN 5-31At command issuance (I/O registers setting contents)1F7H(CM) 100100011F6H(DH)×××DV Max. head No.1F5H(CH)1F4H(CL)1

Interface5-32 C141-E042-01ENAt command issuance (I/O registers setting contents)1F7H(CM) 111011001F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H(

5.3 Host CommandsC141-E042-01EN 5-33Word Value Description21 X’0000’ Undefined22 X’0004’ Number of ECC bytes transferred at READ LONG orWRITE LONG co

Interface5-34 C141-E042-01ENWord Value Description81 X’0000’ Minor version number (not reported)82 X’000B’ Support of command sets *1283 X’4000’ Supp

5.3 Host CommandsC141-E042-01EN 5-35*4 Word 27-46: Model name;ASCII code (40 characters, Left-justified), remainder filled with blank code(X’20’)One

Interface5-36 C141-E042-01ENTable 5.4 Information to be read by IDENTIFY DEVICE COMMAND (3 of 3)*9 Word 63: Multiword DMA transfer modeBit 15-8: Curre

5.3 Host CommandsC141-E042-01EN 5-37Bit 0 = 1 Mode 0*14 WORD 128Bit 15-9: ReservedBit 8: Security level. 0: High, 1: MaximumBit 7-5: ReservedBit

Interface5-38 C141-E042-01EN(14) SET FEATURES (X’EF’)The host system issues the SET FEATURES command to set parameters in theFeatures register for th